1. Field of the Invention
The present invention relates to a signal processing apparatus having at least a central processing unit (CPU) and a non-volatile memory capable of being rewritten from the outside and a programming method of the non-volatile memory.
2. Description of the Related Art
In recent years, along with the improvement of the technology for production of semiconductors, semiconductor devices with high integration and high density are becoming easier to realize. For example, a large number of semiconductor devices have been realized by integration of CPUs and memories and other different types and applications of semiconductor circuits on a single substrate such as with application-specific integrated circuits (ASIC).
As an example of such a semiconductor device, there is for example a semiconductor device with a CPU and a non-volatile memory for storing a program for controlling the operation of the CPU and further a memory to and from which ordinary data is written and read, for example, an SRAM, formed together on its substrate. In this, as the non-volatile memory for storing the program, for example, there are a read-only memory (ROM) or an EEPROM or flash EEPROM which are capable of rewriting and storing written data semipermanently.
In such a semiconductor device, by rewriting the program stored in the non-volatile memory in accordance with need from the outside, a programmable semiconductor device can be realized, different functions can be realized in response to the requests of users, and a semiconductor device of a high flexibility can be provided.
In such programmable semiconductor devices, there are different types of rewritable non-volatile memories. The rewriting routines differ depending on the type. In the past, the rewriting had been carried out according to the rewriting routines inherent to the semiconductor devices. Here, the program for performing the rewriting routine is called a data rewriting program. That is, generally, it is necessary to prepare a rewriting program for each semiconductor device using a different type of non-volatile memory.
In order to rewrite the programming codes, data, and so forth stored in the non-volatile memory of a semiconductor device (hereinafter simply referred to as xe2x80x9cdataxe2x80x9d for convenience), usually a writing device is connected to the semiconductor device to be rewritten and that writing device is used to rewrite the data while as controlling the operation of the CPU in the semiconductor device. Note that the data rewriting being referred to here includes, for example, erasure of data, partial erasure, verification after writing, and so forth according to need depending on the type of the non-volatile memory.
As one example of a rewriting device of a non-volatile memory in a semiconductor device, there is the art disclosed in Japanese Unexamined Patent Publication (Kokai) No. 5-189584. In this example, a data rewriting program is loaded in advance into the semiconductor device. Namely, a memory, for example, a ROM, for storing the data rewriting program is provided in the semiconductor device. When rewriting the data, a CPU loads the data rewriting program from the ROM, then controls the data rewriting in accordance with the loaded program.
FIG. 1 shows an example of the configuration of a system constituted by a semiconductor device and a writing device for rewriting data to the semiconductor device. As illustrated, the semiconductor device 10a is constituted by a microprocessor 20a, a switch 30, functional circuits 40, 50, and a connector 70. The writing device 60 transfers writing data to the microprocessor 20a through the connector 70 to provide rewriting data and commands necessary for data rewriting to the microprocessor 20a. 
The microprocessor 20a is constituted by a ROM switching circuit 21, a flash EEPROM 22, a data receiver (UART) 23, a CPU 24, a ROM (Boot ROM) 25, and an SRAM 26.
Each component circuit in the microprocessor 20a mentioned above transfers data and control signals through a data bus and control signal line (hereinafter simply referred to as a xe2x80x9cbusxe2x80x9d for convenience). Furthermore, the microprocessor 20a transfers data or control signals with the functional circuits 40 and 50 through the same bus 100.
In the microprocessor 20a, the data receiver 23 receives data from the writing device 60 and transfers it to the CPU 24 through the bus 100.
The CPU 24 outputs the data or control signals to the other component circuits through the bus 100 to control the operations of the component circuits.
The ROM switching circuit 21 outputs an enable signal for enabling the flash EEPROM (hereinafter referred to as flash memory) 22 or the ROM 25 in accordance with a switching signal S30 from the switch 30.
The flash memory 22 stores commands or other data for controlling the operation of the CPU 24. Note that the stored data in the flash memory 22 is rewritten based on the control of the writing device 60.
The ROM 25 stores the data rewriting program.
The SRAM 26 temporarily holds the data transferred through the bus 100 and outputs the held data to the other component circuits.
During ordinary operation, a signal S30 having a certain fixed level is output from the switch 30. The ROM switching circuit 21 outputs the enable signal to the flash memory 22 accordingly. In this case, during the initialization of the semiconductor device 10a, the CPU 24 loads commands and data from the flash memory 22 selected by the ROM switching circuit 21, then operates in accordance with the loaded commands. For example, the CPU 24 controls the operations of the functional circuits 40 and 50 through the bus 100 to realize a desired function.
The data is rewritten by the routine shown in the flow chart of FIG. 2. In data rewriting, a control signal Sc for switching the switch 30 is input from the writing device 60. Accordingly, the switch 30 switches (step SS1) and outputs a signal S30 different from that of the ordinary operation.
The ROM switching circuit 21 outputs the enable signal to the ROM 25 according to the signal S30 from the switch 30. Consequently, after the initialization of the semiconductor device 10a (step SS2), the data rewriting program is loaded from the ROM 25 selected by the ROM switching circuit 21 (step SS3) and the rewriting is controlled in accordance with the loaded commands. For example, the CPU 24 communicates with the writing device 60 through the data receiver 23 (step SS4), erases the flash memory 22 (step SS5), then once stores the rewriting data input from the writing device 60 into the SRAM 26 (step SS7), then writes the rewriting data stored in the SRAM 26 to the flash memory 22 (step SS8). Then, the CPU 24 judges whether the writing is finished or not (step SS9) and, if it is not finished, returns to step SS6, where it receives the next writing data from the writing device 60 and writes it into the flash memory 22.
When the data rewriting of the flash memory 22 is carried out normally, the CPU 24 switches the switch 30, and the ROM switching circuit 21 selects the flash memory 22 (step SS10). Accordingly, after the initialization of the semiconductor device 10a (step SS11), the rewritten program and data are loaded to the CPU 24 from the flash memory 22, and the system starts (step SS12).
In the flow chart of FIG. 2, in the operations from steps SS3 to SS9, the CPU 24 is controlled by the rewriting program loaded from the ROM 25. During this period, the program or data in the flash memory 22 is rewritten by the new program or data input from the writing device 60. In the other operation steps, the CPU 24 is controlled by the program loaded from the flash memory 22. Especially, in steps SS10 to SS12 after the data rewriting, the CPU 24 is controlled by the rewritten program in flash memory 22.
However, in the above-mentioned conventional semiconductor device, it is necessary that the ROM 25 storing the data rewriting program be mounted on the substrate in advance. It is also possible to store the data rewriting program in, for example the flash memory instead of the ROM, but in this case, part of the capacity of the flash memory mounted on the substrate is used for the data rewriting program and therefore there is a demerit that the effective capacity of the flash memory is decreased.
Further, a switch for switching the starting ROM is necessary for carrying out the data rewriting after mounting on the substrate. Hardware resources are therefore necessary. Further, since the data rewriting after mounting on the substrate is actually performed by switching the starting ROM by switching jumper wires and so forth, the data rewriting and the restarting of the CPU afterward become troublesome. Further, it is necessary to provide special terminals, connectors, and interconnections on the substrate for transferring the rewriting data, which results in an increase of the mounting area of the substrate. Further, since the routines for data rewriting differ from each other in accordance with the type of the non-volatile memory, there is a disadvantage that when the type of the non-volatile memory changes, it is necessary to change the rewriting program accordingly.
In recent years, along with the spread of the JTAG (Joint Test Action Group) standards, there has been increasing demand for substrate tests and chip tests on system substrates by boundary scan tests. Boundary scan tests are being used in connection tests between chips on a system substrate and tests inside chips.
When applying a boundary scan test to a chip including a CPU, generally both special hardware for rewriting the non-volatile memory and special hardware for the boundary scan test must be mounted on the substrate or on the chip including the CPU. FIG. 3 shows an example of the configuration of a semiconductor device provided with both hardware for data rewriting and hardware for a boundary scan test.
As illustrated in FIG. 3, the CPU 24 is provided with a boundary scan register 27 for carrying out the boundary scan test. Further, the functional circuits 40 and 50 are provided with boundary scan registers 42 and 52 for carrying out the boundary scan test, respectively. These boundary scan registers are connected to a boundary scan test device 80 through a special terminal 90. In the semiconductor device 10b of the present example, hardware for data rewriting, for example, the switch 30, the ROM switching circuit 21, and the connector 70, and hardware for the boundary scan test, for example, the connector 90, are provided separately. Consequently, the mounting area of the substrate increases. Furthermore, there is a waste of the hardware resources considering the fact that the data rewriting and the boundary scan test are normally separately carried out.
The present invention was made in consideration with such a circumstance and has as an object thereof to provide a signal processing apparatus making joint use of hardware resources for data rewriting and a boundary scan test so as to enable a reduction in the waste of the hardware resources, enable realization of a decrease of the substrate area, and enable flexible handling of the rewriting of different types of non-volatile memories, and a programming method thereof.
To achieve the above object, the signal processing apparatus of the present invention is a signal processing apparatus having at least a boundary scan chain for carrying out a boundary scan test, a central processing unit capable of being controlled by the boundary scan chain, a non-volatile memory for storing an operating program of the central processing unit and necessary data, and an input terminal for inputting data and other control signals from the outside to the boundary scan chain; wherein the semiconductor device further comprises a register for holding data transferred from the boundary scan chain and being read for the held data by the central processing unit and a memory for holding the data read from the register; a rewriting program is input via the input terminal from a writing device to the boundary scan chain and then stored in the memory through the register during data rewriting based on the control of the boundary scan chain; and the central processing unit inputs rewriting data through the input terminal and the boundary scan chain to write it into the non-volatile memory based on the control of the rewriting program stored in the memory.
Further, in the present invention, preferably the central processing unit reads the rewriting data from the register and stores the same in the memory then writes the rewriting data stored in the memory in a predetermined area of the non-volatile memory after the erasing operation.
Further, the present invention provides a programming method of a signal processing apparatus having at least a boundary scan chain for carrying out a boundary scan test, a central processing unit capable of being controlled by the boundary scan chain, a non-volatile memory for storing an operating program of the central processing unit and necessary data, and an input terminal for inputting data and other control signals from the outside to the boundary scan chain, comprising the steps of inputting a rewriting data program for controlling the rewriting operation of the non-volatile memory from a writing device connected to the input terminal to the boundary scan chain and reading out and storing into the memory the rewriting program transferred from the boundary scan chain, inputting rewriting data to be written into the non-volatile memory from the writing device through the input terminal and the boundary scan chain and storing the same in the memory by the central processing unit based on the control of the rewriting program stored in the memory, and writing the rewriting data stored in the memory to a predetermined area of the non-volatile memory after erasing the predetermined area.
Further, in the present invention, preferably, when the volume of the rewriting data is greater than the capacity of the memory, operations of inputting a portion of the rewriting data from the writing device, storing the portion of the rewriting data to the memory, and writing the portion of the rewriting data stored by the memory into the non-volatile memory are repeated until the rewriting data is completely written to the non-volatile memory by the central processing unit based on the control of the rewriting program.
According to the present invention, there is provided a signal processing apparatus comprising hardware for a boundary scan test which utilizes the hardware for the boundary scan test for data rewriting of the non-volatile memory built in the signal processing apparatus so as to share the hardware resources and reduce the chip area of the signal processing apparatus. More specifically, when rewriting data in the non-volatile memory, a data writing device is connected to a special input terminal for the boundary scan test, and a rewriting program for controlling the rewriting operation is input to the boundary scan chain by the data writing device. The rewriting program transferred by the boundary scan chain is read out from the central processing unit (CPU) through the register and then stored in the memory. After that, the CPU controls the data rewriting operation based on the control of the rewriting program stored in the memory. Due to this, a certain area of the non-volatile memory is erased, rewriting data is input from the writing device to the non-volatile memory and temporarily stored in the memory, then the stored data is written into the non-volatile memory. When the volume of the rewriting data of the non-volatile memory is larger than the storage capacity of the memory, since the operations of inputting part of the rewriting data, storing it in the memory, then writing it into the non-volatile memory are carried out repeatedly, the rewriting data is written into the non-volatile memory successively over several times.